Dynamically Partitioned Test Scheduling for SoCs Under Power Constraints

Test scheduling increases parallelism of test application and reduces the test cost. In this paper, we present a novel scheduling algorithm for testing embedded core-based System-on-Chips. Given a system integrated with a set of cores and a set of test resources, we construct a set of power constrained concurrent test sets from a power-constrained test compatibility graph (P-TCG). Furthermore, we schedule the tests in a way that dynamically partitions and allocates the tests, and consequently constructs and updates a set of dynamically partitioned PCTS’s, and ultimately reduces the test application time. Simulation results show that the proposed approach achieves better performance than existing comparable scheduling algorithms.